TI Processor Allocation in a Multi-ring Dataflow Machine 

AU Pedro Barahona 

AU John R. Gurd 

LT UMCS-85-10-3 

OR UMCS 

AV http
http:www.cs.man.ac.ukcsonlycstechrepAbstractsUMCS-85-10-3.html 

AV email techreports@cs.man.ac.uk 

MN October 

YR 1985 

AB Partitioning a program into processes and allocating these
processes to different processors determines the efficiency of a
multiprocessor architecture.  In the dataflow model, where each
process consists of a single instruction (e.g. an arithmetic or
logic operation), an automatic decomposition of a program into
fine-grain processes can be achieved. A prototype dataflow
machine is in operation at the University of Manchester.  The
machine comprises a single processing element (PE), which
contains several units connected together in a pipelined ring.  A
Multi-ring Dataflow Machine (MDM), containing several such
processing elements connected together via a switching network,
is currently under investigation. _
    This paper describes a method of allocating the dataflow
instructions to the processing elements of the Multi-ring
Dataflow Machine and examines the influence of the method on the
selection of a switching network.  Results obtained from
simulation of the machine are presented, and it is shown that
programs are executed efficiently when their parallelism matches
the parallelism of the machine hardware.